In digital transmission systems it is desirable to recover a clock signal from an incoming data stream and use that clock to re-time the received data. Ideally, this recovered clock is frequency locked to the data line rate and exhibits no additional jitter.
Various techniques for accomplishing this result are taught in the prior art. Known clock recovery systems typically utilize a digital phase locked loop in which a phase detector compares the data signal to the recovered clock signal, and produces an error signal indicative of a phase and/or frequency difference between the data and recovered clock signals. The error signal is used to control a numerically or voltage controlled oscillator that generates the recovered clock signal. Typically, a frequency lock condition is detected by comparison between the recovered clock signal and a network reference clock signal. It is also common practice to arrange the phase locked loop such that the oscillator will generate a recovered clock signal frequency locked to the network reference clock in the absence of a received data signal.
The prior art clock recovery systems are capable of maintaining phase and frequency lock between the data signal (or reference clock signal) and the recovered clock signal (oscillator output) within the pull-in range of the phase locked loop. Typically, this pull-in range is on the order of 1000 parts per million (ppm), which is adequate for digital transmission protocols having a narrow tolerance in the acceptable line transmission rate. Thus the network reference clock can be set to the nominal line transmission rate defined for the transmission protocol, and the oscillator controlled to produce a recovered clock signal which is frequency locked to the network reference clock. When a data signal is subsequently received, its frequency (provided that it is within the defined tolerances for the particular transmission protocol) will be within the pull-in range of the phase-locked loop, so that the oscillator can be controlled to pull-in the recovered clock signal to achieve a phase and frequency locked condition with the data signal.
However, emerging digital transmission protocols have wide tolerances in the acceptable line rate, well beyond the pull-in range of conventional methods of clock recovery systems. Previous proposals for wide-band frequency acquisition do not meet the jitter requirements for large, cascaded networks. In addition, none of these prior art systems provides an accurate and robust measure of the quality of the data. Consequently, no assurance is given that the data signal has a fixed line transmission rate and is within the wide-band specification of the transmission protocol.
In some applications there are additional features which conventional clock recovery systems do not address. First, it is desirable to determine when a received data signal has failed, and subsequently lock the oscillator to a fixed frequency until the data signal has recovered. Second, while the frequency is fixed, it is necessary to determine when the data signal has recovered and subsequently allow the recovered clock signal to track the data. Finally, it is desirable for the clock recovery unit to be able to pull-in to any frequency within a broad range. Conventional clock recovery systems do not address these features.
Accordingly, there remains a need for a clock recovery unit (CRU) that enables phase and frequency pull-in to data signals, the CRU having wide tolerances in acceptable line transmission rate, as well as protocol-independent detection of data signal failure and recovery.